A Digital Circuit for Jitter Reduction of GPS-disciplined 1-pps Synchronization Signals

Abstract – The Global Positioning System (GPS) satellites transfer accurate time from atomic clocks, thus enabling the receivers on Earth to produce high-stability synchronization signals (i.e., trains of low-jitter pulses without drift). The timing accuracy of the generated stream of pulses depends on the features as well as on the cost of the specific GPS receiver employed. This paper describes a fully digital synchronization circuit that is able to reduce the jitter associated to the 1 pulse per second (1-pps) signal generated by a typical low-cost receiver of moderate timing accuracy within a short settling time interval. The proposed circuit has been implemented using an FPGA and the jitter reduction has been estimated experimentally

A Scalable Approach for Supporting Streaming Media: Design, Implementation and Experiments

Future Internet traffic will be dominated by ondemand streaming media flows, such as IPTV, 3D/HD video, gaming, virtual reality, and many more. Consequently, future network architectures will need to offer predictable performances to such applications. In order to achieve scalable IP packet switching it is essential to minimize “stopping ” of the serial bit streams, in order to minimize: buffer size, jitter and loss. Our recent experimental work demonstrated how an IP network can be implemented without “stopping” the serial bit streams. Consequently, the switch realized is very simple, scalable to 10-100 terabits per second in a single chassis, and suitable for all optical implementation. The implemented testbed uses only off-the-shelf optical and electronic components and was completed in 9-month. 1